In the prior art, there is a method in which a wiring substrate is obtained by forming a multilayer wiring including connection pads on a supporting plate, and removing the supporting plate to expose the connection pads. Such wiring substrate is manufactured in many cases in a state that surfaces of the connection pads and a surface of an insulating layer constitute the same plane.
As a result, there is such a risk that, in the situation that a pitch of the connection pads of the wiring substrate is made narrower, when a semiconductor chip is flip-chip connected to the connection pads by the solder, the solder flows from the connection pad to the lateral direction to cause an electric short-circuit between the connection pads.
Also, the surface of the wiring substrate on the connection pad side is made flat. Therefore, the accuracy of image recognition of fiducial marks provided on the surface of the wiring substrate on the connection pad side is bad. As a result, it becomes difficult to align and mount the semiconductor chip, or the like with high precision.
A related art is disclosed in International Publication Pamphlet No. WO 2008-001915.